(a) Field of the Invention
The invention relates to a digital display device, particularly to a digital television display device.
(b) Description of the Related Art
In modern life, display control technology has become indispensable for daily life. Accompanying with the technology improvement and the opening of media, the channel that can be received by the display device (such as: the television) is also becoming more various.
Currently, there are basically two types of digital display control technologies. The first type is the frame rate conversion, that is, the data of at least one frame is buffered by the frame buffer and is displayed after processing. Therefore, the timing control of the output image signal is completely irrelevant to the input image signal. However, the chip area increases due to the large storage capacity of the frame buffer and thereby the cost increases. The second type is the frame synchronization, that is, the data of less than one frame is buffered by the line buffer and is displayed after processing. Since the buffered image data is less than one frame, the frame rates of the input frame and the output frame must be maintained at a specific relation in order to avoid the line buffer overflow or underflow. Therefore, the output image signal timing has specific relations with the input image signal timing. In order to establish the specific relation between the output image signal and the input image signal frame rate, a display vertical synchronization (DVS) signal is generally initiated according to an input vertical synchronization (IVS) signal. The method according to the prior art resets the DVS signal and then outputs the DVS signal according to the IVS signal.
During channel switching, since the video signal timing of the two channels are irrelevant with each other, the frequencies and the phases of the IVS signals of the two channels are most likely not the same. Please refer to FIG. 1, where the IVS signal of the channel 1 is not synchronizing with the IVS signal of the channel 2. However, the frame synchronization technology resets the DVS signal according to the IVS signal. The channel switching may result in such DVS signal timing shown in FIG. 1. Since the DVS signal format (that is, the frame timing) resulting from Such phenomenon cannot meet the required timing of the panel, the panel cannot display normally.
Therefore, an invention for solving the above-mentioned problems is needed urgently.